1. Field of the Invention
The present invention relates generally to the field of semiconductor chip processing or integrated circuit (IC) fabrication. More particularly, the present invention is related to an interlayer dielectric and the processing steps associated with the interlayer dielectric.
2. Description of the Related Art
Integrated circuits (ICs) often include a number of conductive or metal layers separated by insulative or dielectric layers. The metal layers are generally provided over an insulative layer (ILDO) that covers transistors disposed in a substrate. Each metal layer or stack generally is a composition of several conductive materials, such as, tantalum (Ta), copper (Cu), aluminum (Al), titanium (Ti), tungsten (W), and compounds of copper, tantalum, aluminum, tungsten, nitrogen (N), and titanium. The dielectric layers are generally silicon dioxide (SiO2) and are often referred to as interlayer dielectrics or interlevel insulators. The interlayer dielectrics electrically isolate metal layers from each other (e.g., a metal 1 layer from a metal 2 layer).
The interlayer dielectric is typically deposited as silicon dioxide in a chemical vapor deposition (CVD) process. For example, the interlayer dielectric can be provided over a metal layer in a tetraorthosilicate (TEOS) process. After the interlayer dielectric is planarized, a metal layer is provided over the interlayer dielectric.
Generally, it is desirable to reduce the capacitance associated with the metal layers in an IC. Reducing capacitance increases the speed of the IC and is a particularly important design goal as IC devices become smaller. One technique for reducing the capacitance associated with the metal layers is to reduce the dielectric constant associated with the interlayer dielectric (e.g., the insulating layer between metal layers).
Fluorinated silicon dioxide (SiOF) material can be used as the interlayer dielectric instead of silicon dioxide material to lower the capacitance associated with the metal layers. Fluorinated silicon dioxide has a lower dielectric constant than silicon dioxide. For example, fluorinated silicon dioxide has a dielectric constant in a range from 3.6 to 3.8, while silicon dioxide has a dielectric constant of 4.0 or more. Fluorinated silicon dioxide is typically provided by plasma enhanced chemical vapor deposition (PECVD) or a high density plasma (HDP) application technique. Therefore, utilizing fluorinated silicon dioxide can reduce the capacitance associated with the semiconductor device and thereby increase its speed and performance.
Fluorine atoms in fluorinated silicon dioxide can react with barrier metals (Ti, TiN, Ta, TaN, Al, Cu, etc) associated with the metal layers. The barrier metals are typically deposited (BMD) by plasma vapor deposition (PVD) or chemical vapor deposition (CVD) on the surface of the fluorinated silicon dioxide. For example, in an IC containing two metal layers, a barrier metal for the second metal layer is deposited on the interlayer dielectric which covers the first metal layer. The barrier metal layer is typically located on the bottom of the composite metal layer. The reaction between the fluorine and the barrier metal can cause delamination and other adhesion problems.
In addition, the reaction can cause delamination and adhesion problems inside vias (e.g., holes) which extend through the fluorinated silicon dioxide. Contacts or electrical connections between metal layers are made through vias in the interlayer dielectric. Delamination and adhesion problems can also exist at the interface between the titanium nitride layer and the fluorinated silicon dioxide layer. The titanium and titanium nitride layers are typically located at the top of the composite metal layers.
Thus, there is a need for an IC which is less susceptible to adhesion and delamination problems. Further still, there is a need for a method of manufacturing an IC that reduces adhesion and delamination problems associated with fluorinated silicon dioxide.